The operation speeds of microcomputer's semiconductor circuits, which includes processing units, a main storage, and an I/O interface have improved in recent years. These processing units are connected to one another through a bus. Bus access speed sometimes limits the performance of the processing units when the processing units frequently access the main storage and I/O interface through the bus.
FIG. 1 is a timing chart showing a bus control system according to the prior art.
In the figure, one processing unit provides a data access request for accessing another processing unit that may be a main storage. An internal bus access signal is changed from a high logic to a low logic, and according to this change, an access request signal (HREQ#) is asserted. Here, the mark "#" indicates that the signal is active low.
The signal HREQ# is sent to, for example, an arbiter circuit that arbitrates a bus right. If the bus right is free, the arbiter circuit provides a bus right acquisition acknowledge signal (HACK#).
Upon receiving the signal HACK#, the processing unit becomes a bus master having the bus right to access the main storage to write and read data.
When the signal HREQ# is negated, the arbiter circuit recognizes this and negates the signal HACK# to release the bus right.
Transferring the two signals (HREQ# and HACK#) is called "bus arbitration."
This kind of conventional bus control system carries out the bus arbitration whenever a bus request is raised, so that, when the bus request is repeatedly issued, a bus access wait time is prolonged to deteriorate processing performance.
The bus access wait time is a time from asserting the signal HREQ# to receiving the asserted HACK# (a time ta in FIG. 1) and a time from providing a bus request to asserting the signal HREQ# (a time tb in FIG. 1).
A wait time Et accompanied by a single bus request is expressed as follows: EQU .SIGMA.t=ta
A wait time .SIGMA.tn for n times of bus requests is expressed as follows: EQU .SIGMA.tn=(ta. n)+{tb.(n-1)}
Namely, as the number of bus requests increases, the wait time becomes longer. This may hinder the performance of a processing unit, i.e., a bus request source that frequently accesses the storage means.
FIG. 2 shows two processing units (A and B) sharing a memory 10 through a common bus 1. When the processing unit B frequently accesses the memory, the efficiency of the system as a whole may deteriorate because the bus arbitration takes a long time.
An object of the invention is to reduce the bus access wait time and improve the performance of a processing unit, i.e., a bus request source that frequently accesses a storage means.